Differenze
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| * [[vlsi:resources:books#digital_electronics_and_logic_design|Digital electronics and logic design]] | * [[vlsi:resources:books#digital_electronics_and_logic_design|Digital electronics and logic design]] | ||
| * [[vlsi:resources:books#verilog_and_vhdl_programming|Verilog and VHDL programming]] | * [[vlsi:resources:books#verilog_and_vhdl_programming|Verilog and VHDL programming]] | ||
| - | * [[vlsi:resources:books#digital_ic_design|Digital IC design]] | + | * [[vlsi:resources:books#digital_synthesis|Digital synthesis]] |
| + | * [[vlsi:resources:books#digital_cmos_ic_design|Digital CMOS IC design]] | ||
| * [[vlsi:resources:books#vlsi_design_and_layout|VLSI design and layout]] | * [[vlsi:resources:books#vlsi_design_and_layout|VLSI design and layout]] | ||
| * [[vlsi:resources:books#fpga_programming|FPGA programming]] | * [[vlsi:resources:books#fpga_programming|FPGA programming]] | ||
| Linea 68: | Linea 69: | ||
| * P. Horowitz and W. Hill, //The Art of Electronics// [x] 1980 1st ed., 1989 2nd ed. | * P. Horowitz and W. Hill, //The Art of Electronics// [x] 1980 1st ed., 1989 2nd ed. | ||
| * G.J. Ritchie, //Transistor Circuit Techniques: Discrete and Integrated// [x] | * G.J. Ritchie, //Transistor Circuit Techniques: Discrete and Integrated// [x] | ||
| - | * D.L. Eggleston , //Basic Electronics for Scientists and Engineers// [x] | + | * D.L. Eggleston, //Basic Electronics for Scientists and Engineers// [x] |
| + | * E. Sicard, S. D. Bendhia, //Basics of CMOS Cell Design-McGraw-Hill Professional (2007)// [x] | ||
| ====== Practical electronics ====== | ====== Practical electronics ====== | ||
| Linea 114: | Linea 116: | ||
| * M.J. Buckingham, //Noise in Electronics Devices and Systems// | * M.J. Buckingham, //Noise in Electronics Devices and Systems// | ||
| * S.O. Rice, //Mathematical Analysis of Random Noise// | * S.O. Rice, //Mathematical Analysis of Random Noise// | ||
| + | * J.F. Witte, K.A.A. Makinwa, J.H. Huijsing, //Dynamic offset compensated CMOS amplifiers// | ||
| ====== Information and Coding Theory ====== | ====== Information and Coding Theory ====== | ||
| Linea 167: | Linea 169: | ||
| ====== PLLs and SC circuits ====== | ====== PLLs and SC circuits ====== | ||
| - | * B. Razavi, //Monolithic Phase-Locked Loops and Clock Recovery Circuits// | + | * B. Razavi, //Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design// |
| * R.E. Best, //Phase-Locked Loops: Design, Simulation and Applications// | * R.E. Best, //Phase-Locked Loops: Design, Simulation and Applications// | ||
| * P.E. Allen and E. Sánchez-Sinencio, //Switched Capacitor Circuits// | * P.E. Allen and E. Sánchez-Sinencio, //Switched Capacitor Circuits// | ||
| Linea 191: | Linea 193: | ||
| * R.K. Brayton et al., //Logic Minimization Algorithms for VLSI Synthesis// [x] | * R.K. Brayton et al., //Logic Minimization Algorithms for VLSI Synthesis// [x] | ||
| * P.K. Lala, //Principles of Modern Digital Design// | * P.K. Lala, //Principles of Modern Digital Design// | ||
| + | * R.F. Tinder, //Asynchronous Sequential Machine Design and Analysis: A Comprehensive Development of the Design and Analysis of Clock-Independent State Machines and Systems// | ||
| + | * J. Bainbridge, //Asynchronous System-on-Chip Interconnect// | ||
| + | * H. Bhatnagar, //Advanced ASIC Chip Synthesis Using Synopsys Tools// | ||
| + | * H. Bhathagar, //Advanced ASIC Chip Synthesis Using Synopsys, Design Compiler and PrimeTime// | ||
| ====== Verilog and VHDL programming ====== | ====== Verilog and VHDL programming ====== | ||
| Linea 226: | Linea 231: | ||
| * J. Bergeron, //Writing Testbenches: Functional Verification of HDL Models// [x] | * J. Bergeron, //Writing Testbenches: Functional Verification of HDL Models// [x] | ||
| + | |||
| + | |||
| + | ====== Digital synthesis ====== | ||
| + | |||
| + | * S. Gangadaran and S. Churiwala, //Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC)// [x] | ||
| ======= Digital CMOS IC design ======= | ======= Digital CMOS IC design ======= | ||
| Linea 342: | Linea 352: | ||
| * W.R. Leo, //Techniques for Nuclear and Particle Physics Experiments// [x] | * W.R. Leo, //Techniques for Nuclear and Particle Physics Experiments// [x] | ||
| * R.S. Gilmore, //Single Particle Detection and Measurement// | * R.S. Gilmore, //Single Particle Detection and Measurement// | ||
| + | * F. Hartmann, //Evolution of silicon sensor technology in particle physics// [x] | ||
| ====== Silicon detectors and radiation hardness ===== | ====== Silicon detectors and radiation hardness ===== | ||
| Linea 365: | Linea 376: | ||
| * M. L. Bushnell, V. D. Agrawal //Essentials of Electronic Testing For Digital Memory and Mixed-Signal VLSI Circuits// [x] | * M. L. Bushnell, V. D. Agrawal //Essentials of Electronic Testing For Digital Memory and Mixed-Signal VLSI Circuits// [x] | ||
| * K. P. Parker, //The boundary scan handbook// [x] | * K. P. Parker, //The boundary scan handbook// [x] | ||
| + | * L-T. Wang, C-W. Wu, X. Wen, //VLSI Test Principles and Architectures // [x] | ||
| ====== ====== | ====== ====== | ||
| Linea 370: | Linea 382: | ||
| ---- | ---- | ||
| - | Last update: [[pacher@NOSPAMto.infn.it|Luca Pacher]] - Dec 7, 2013 | + | Last update: [[pacher@NOSPAMto.infn.it|Luca Pacher]] - Feb 1, 2015 |
| ~~NOTOC~~ | ~~NOTOC~~ | ||