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vlsi:resources:books [24/09/2014 00:05] pacher |
vlsi:resources:books [01/07/2015 18:04] cenna |
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* P. Horowitz and W. Hill, //The Art of Electronics// [x] 1980 1st ed., 1989 2nd ed. | * P. Horowitz and W. Hill, //The Art of Electronics// [x] 1980 1st ed., 1989 2nd ed. | ||
* G.J. Ritchie, //Transistor Circuit Techniques: Discrete and Integrated// [x] | * G.J. Ritchie, //Transistor Circuit Techniques: Discrete and Integrated// [x] | ||
- | * D.L. Eggleston , //Basic Electronics for Scientists and Engineers// [x] | + | * D.L. Eggleston, //Basic Electronics for Scientists and Engineers// [x] |
+ | * E. Sicard, S. D. Bendhia, //Basics of CMOS Cell Design-McGraw-Hill Professional (2007)// [x] | ||
====== Practical electronics ====== | ====== Practical electronics ====== | ||
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* A. S. Tanenbaum, //Modern Operating Systems [International Vers.]// [x] | * A. S. Tanenbaum, //Modern Operating Systems [International Vers.]// [x] | ||
* A. S. Tanenbaum, //Structured Computer Organization// [x] | * A. S. Tanenbaum, //Structured Computer Organization// [x] | ||
+ | * S. Haykin, // Communication Systems, 4th ed. // [x] | ||
====== Analog and mixed-mode IC design ====== | ====== Analog and mixed-mode IC design ====== | ||
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* P.G. Jespers, //The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits// [x] | * P.G. Jespers, //The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS Circuits// [x] | ||
* A. Wang, B.H. Calhoun and A.P. Chandrakasan, //Sub-Threshold Design for Ultra Low-Power Systems// [x] | * A. Wang, B.H. Calhoun and A.P. Chandrakasan, //Sub-Threshold Design for Ultra Low-Power Systems// [x] | ||
- | * D.M. Binkley, //Tradeoffs and Optimization in Analog CMOS Design// | + | * D.M. Binkley, //Tradeoffs and Optimization in Analog CMOS Design// [x] |
====== OP-AMPs and comparators ====== | ====== OP-AMPs and comparators ====== | ||
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====== PLLs and SC circuits ====== | ====== PLLs and SC circuits ====== | ||
- | * B. Razavi, //Monolithic Phase-Locked Loops and Clock Recovery Circuits// | + | * B. Razavi, //Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design// |
* R.E. Best, //Phase-Locked Loops: Design, Simulation and Applications// | * R.E. Best, //Phase-Locked Loops: Design, Simulation and Applications// | ||
* P.E. Allen and E. Sánchez-Sinencio, //Switched Capacitor Circuits// | * P.E. Allen and E. Sánchez-Sinencio, //Switched Capacitor Circuits// | ||
Linea 190: | Linea 192: | ||
* R.K. Brayton et al., //Logic Minimization Algorithms for VLSI Synthesis// [x] | * R.K. Brayton et al., //Logic Minimization Algorithms for VLSI Synthesis// [x] | ||
* P.K. Lala, //Principles of Modern Digital Design// | * P.K. Lala, //Principles of Modern Digital Design// | ||
+ | |||
====== Verilog and VHDL programming ====== | ====== Verilog and VHDL programming ====== | ||
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* F. Vahid, //Verilog for Digital Design// | * F. Vahid, //Verilog for Digital Design// | ||
* Z. Navabi, //Verilog Digital System Design// | * Z. Navabi, //Verilog Digital System Design// | ||
+ | * J. Williams, // Digital VLSI design with Verilog// [x] | ||
Linea 211: | Linea 215: | ||
* K.C. Chang, //Digital Systems Design with VHDL and Synthesis// [x] | * K.C. Chang, //Digital Systems Design with VHDL and Synthesis// [x] | ||
* S. Brown, Z. Vranesic, //Fundamentals of Digital Logic with VHDL Design// [x] | * S. Brown, Z. Vranesic, //Fundamentals of Digital Logic with VHDL Design// [x] | ||
- | * P.J. Ashenden 1990, //The VDHL Cookbook// [[http://esd.cs.ucr.edu/vhdlcook/]] [x] | + | * P.J. Ashenden 1990, //The VHDL Cookbook// [[http://esd.cs.ucr.edu/vhdlcook/]] [x] |
- | * P.J. Andersen, Morgan Kaufman Publisher, //The Designer's Guide to VHDL// [x] | + | * P.J. Ashenden, Morgan Kaufman Publisher, //The Designer's Guide to VHDL// [x] |
* P.P. Chu, //RTL Hardware Design Using VHDL// [x] | * P.P. Chu, //RTL Hardware Design Using VHDL// [x] | ||
* F. Vahid, //VHDL for Digital Design// | * F. Vahid, //VHDL for Digital Design// | ||
Linea 238: | Linea 242: | ||
* B. Razavi, //Design of Integrated Circuits for Optical Communications// [x] | * B. Razavi, //Design of Integrated Circuits for Optical Communications// [x] | ||
* R. Chadha and J. Bhasker, //Static Timing Analysis for Nanometer Designs// | * R. Chadha and J. Bhasker, //Static Timing Analysis for Nanometer Designs// | ||
+ | * D. Stefanovic, M. Kayal, //Structured analog CMOS design// [x] | ||
+ | * P. Jespers, //The gm/Id methodology, a sizing tool for low-voltage analog CMOS circuits// [x] | ||
+ | * D. M. Binkley, //Tradeoffs and Optimization in Analog CMOS Design// [x] | ||
+ | * T. Ytterdal, Y. Cheng, T. A. Fjeldly, //Device Modeling for Analog and RF CMOS Circuit Design// [x] | ||
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====== EDA and CAD engeneering ====== | ====== EDA and CAD engeneering ====== | ||
+ | * E. Brunvad, //[[http://www.cs.utah.edu/~elb/cadbook/|Digital VLSI Chip Design with Cadence and Synopsys CAD Tools]]// [x] | ||
* L. Lavagno, G. Martin and L. Scheffer, //Electronic Design Automation for Integrated Circuits Handbook// | * L. Lavagno, G. Martin and L. Scheffer, //Electronic Design Automation for Integrated Circuits Handbook// | ||
* M. Birnbaum, //Essential Electronic Design Automation (EDA)// | * M. Birnbaum, //Essential Electronic Design Automation (EDA)// | ||
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====== PCB design ====== | ====== PCB design ====== | ||
+ | * K. Mitzner, //Complete PCB Design Using OrCAD Capture and PCB Editor// | ||
* J.M. Kirkpatrick, //Electronic Drafting and Printed Circuit Board Design// | * J.M. Kirkpatrick, //Electronic Drafting and Printed Circuit Board Design// | ||
* R. Khandpur, //Printed Circuit Boards: Design, Fabrication, and Assembly// [x] | * R. Khandpur, //Printed Circuit Boards: Design, Fabrication, and Assembly// [x] | ||
Linea 327: | Linea 343: | ||
* W.R. Leo, //Techniques for Nuclear and Particle Physics Experiments// [x] | * W.R. Leo, //Techniques for Nuclear and Particle Physics Experiments// [x] | ||
* R.S. Gilmore, //Single Particle Detection and Measurement// | * R.S. Gilmore, //Single Particle Detection and Measurement// | ||
+ | * F. Hartmann, //Evolution of silicon sensor technology in particle physics// [x] | ||
====== Silicon detectors and radiation hardness ===== | ====== Silicon detectors and radiation hardness ===== | ||
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* J.K. Ousterhout, //Tcl and the Tk Toolkit// | * J.K. Ousterhout, //Tcl and the Tk Toolkit// | ||
+ | ====== Design for testability ====== | ||
+ | * J. Moreira, H. Werkmann, //An Engineer’s Guide to Automated Testing of High-Speed Interfaces// [x] | ||
+ | * M. Abramovici, M. A. Breuer, A. D. Friedman, //Digital systems testing and testable design// [x] | ||
+ | * M. L. Bushnell, V. D. Agrawal //Essentials of Electronic Testing For Digital Memory and Mixed-Signal VLSI Circuits// [x] | ||
+ | * K. P. Parker, //The boundary scan handbook// [x] | ||
+ | * L-T. Wang, C-W. Wu, X. Wen, //VLSI Test Principles and Architectures // [x] | ||
====== ====== | ====== ====== | ||
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---- | ---- | ||
- | Last update: [[pacher@NOSPAMto.infn.it|Luca Pacher]] - Dec 7, 2013 | + | Last update: [[pacher@NOSPAMto.infn.it|Luca Pacher]] - Feb 1, 2015 |
~~NOTOC~~ | ~~NOTOC~~ |