Modifica questa pagina Puntano qui Rename Page Fold/unfold all Puntano qui Questa è una lista delle pagine che sembrano avere un collegamento alla pagina attuale. Namespace/Gruppi WikiheaderINFN/CSN5Short historyVLSI Design Laboratory Wiki Home PageInfo and coordinatesUseful links and contactsVLSI lab Wiki OutreachpersonalpagesFrancesca Cenna - Wiki personal pageManuel Rolo - Wiki personal pageEnnio Monteil - Wiki personal pageLuca Pacher - Wiki personal pageLuca Pacher /DidatticaEsperimentazioni II - Esercitazioni LTspiceAngelo Rivetti - Wiki personal pageVLSI Lab projects and design activitiesALICE Phase1 ITS upgradeCHIPIX65 Torino activities Wiki Home PageCMS Phase 2 pixel upgrade (RD53/CHIPIX65)VLSI past projectsCMAD chipDACEL/GBTDilbert chipNA62/GtkToLePixTERAPANDA MVD designsThe ToPix ASIC Wiki Home PageCERN RD53 referencesSEED project page (tmp)Time-of-Flight PET (TOF-PET) (template)Ultra-Fast Silicon Detector (UFSD) references (very preliminary!)PublicationsReference books and literatureConferences and WorkshopsFPGA useful referencesLaTex references and templatesCurriculum VitæPapersPostersPresentations with LaTexLaTeX syntax quick referencesVLSI LaTex templatesGuidelines for master and PhD disserationsElectronics lectures and coursesMicroelectronic Devices and Circuits (EE105)Analog Integrated Circuits (EE140/EE240A)Introduction to Digital Integrated Circuits (EE141)Advanced Analog Integrated Circuits (EE240)Advanced Digital Integrated Circuits (EE240)Analog-Digital Interfaces in VLSI Technology (EE247)Electronic Techniques for Engineering/Introduction to Microelectronic Circuits (EE40/42/100)ph.unito electronics courses referencesVLSI students internal meetingsWorkshops and seminarsDATA driven FEE for time and energy measurement with highly segmented detector - course slidesWorkshop on Real time, self triggered front end electronics for multichannel detectors - talksEDA tools official support and trainingSystemVerilog referencesUniversal Verification Methodology (UVM) referencesVerilog referencesVHDL referencesPeople and contactsElectronics lab/VLSI lab theses archiveBachelor thesesMaster thesesPhD thesesTheses opportunitiesVLSI lab technology transfer activitiesAbout this WikiWiki policies and guidelinesvlsi/wiki/usersVLSI Design WorkBookVLSI Design WorkBook [ADVANCED TOPICS]List of most important Cadence environment variablesStandard Delay Format (SDF) annotation and simulationPart II - Analog and mixed-mode IC designAdvanced analog design simulationsMonte Carlo simulations using Cadence ADE XLBad analog design practicesCadence environment and setup filesAnalog IC design FAQsDesign hierarchy in Cadence IC (Virtuoso)Analog IC design HowTo'sNode impedance simulationStandard layout examplesLayout (an introduction)Working with parametrized cellsPost layout simulationsBasic layout techniquesBasic layout tutorialsRunning simulations using OCEANSimulation referencesNoise analyses using CadencePower consumption evaluation in Cadence VirtuosoGetting startedDesign techniquesBasic analog design tutorialsWeb tutorials on analog IC design with CadencePart V - Data analysis and programmingData analysis and programming FAQsData analysis and programming HowTo'sPython and PyROOTUsing ROOT within the VLSI labPart I - Computing environmentAccounts and registrationRunning VLSI design platformsRunning Cadence IC (Virtuoso)Computing resourcesHelp and documentationComputing FAQsComputing HowTo'sBuild your own local development environmentAccessing computing resources remotelyConfiguring PuTTYStarting the X serverSetting up the computing environmentLicensed softwaresTroubleshootingUNIX/Linux references for VLSI lab users and system administratorsUNIX/Linux basic commandsUNIX/Linux system administration references(Another yet) Vidyo tutorialPart III - Digital IC designDigital IC design FAQsDigital design HowTo'sAutomatic place and route with Cadence EncounterBuild a standard cell library from scratchPart VI - FPGA design and programmingGlossaryPart IV - Introduction to mixed-signal IC designPart VIII - Introduction to TCAD simulationsWorkBook tutorialsPart V - Physical verification (DRC/LVS/PEX)Layout verification using AssuraPhysical verification using Calibre