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--- vlsi:analog_simref [07/05/2013 01:30]
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+++ vlsi:analog_simref [22/08/2013 19:55]
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    * [[vlsi:analog_simref#ADE_simulation_options|ADE simulation options]]
    * [[vlsi:analog_simref#node_impedance_simulation|Node impedance simulation]]
+   * [[vlsi:analog_simref#pwl_voltage_and_current_sources|PWL voltage and current sources]]
+   * [[vlsi:analog_simref#noise_analyses|Noise analyses]]
@@ Linea 139: / Linea 141: @@
-===== Voltage/current PWL sources from file =====
+===== PWL voltage and current sources =====
-piecewise linear (PWL) vector values
+piecewise linear (PWL)
-Vpwlf (piece-wise linear from file). The syntax is a column of time values
+Vpwl (piece-wise linear) to be used in **transient simulations**.
-and a column of voltage or current values,
+Values can be also specified into a plain text file and then using
+a **Vpwlf** voltage source, which takes file values and convert them
+to a standard **Vpwl** source.
+**analogLib => Sources => Independent => Vpwlf**
+The syntax is a column of time values and a column of voltage or current values,
 <code>
@@ Linea 155: / Linea 167: @@
 Specify the **full path to the file** or copy it in the same directory of the netlist
+<code>
+cd ~/scratch/<tech_dir>/data
+mkdir vpwlf
+</code>
+Notare che posso anche passare il nome del file ad ADE come variabile, usare
+<code>
+pPar("filename")
+</code>
+nel CDF parameter dell'istanza.
+[[http://www.cadence.com/Community/forums/t/23078.aspx]]
+===== Noise analyses =====
+Both standard AC noise analysis and transient noise analysis. Click [[vlsi:analog_noise_sim|here]].
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