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-====== Part II - Analog and mixed-mode IC design ======
-[ __[[vlsi:home|Home]]__ ]
-[ __[[vlsi:workbook|VLSI Design WorkBook]]__ ]
-[ __[[vlsi:analog_main#contents|Contents]]__ ]
-[ __[[vlsi:webtutorials|Third party tutorials]]__ ]
-[ __[[vlsi:books|Books]]__ ]
-[ __[[vlsi:glossary|Glossary]]__ ]
-[ __[[vlsi:analog_howtos|HowTo's]]__ ]
-[ __[[vlsi:analog_faqs|FAQs]]__ ]
-\\
-The second part of the WorkBook...
-**technology-independent tutorials**
-vanilla environment setups
-simple SPICE model files that can be downloaded without restrictions from the Web
-Although layout exercises have been run attached to a specific technology, no technology
-references will be included in the tutorials description. As a matter of fact we mention
-a few very standard layers (e.g. M1 and M2 metal layers) which are common to all technologies.
-extract a simple **sandwitch metal-to-metal capacitor**, which is another technology-independent example
-== Contents ==
-   * **[[analog_start|Getting started]]**
-      * Introduction
-      * Tools overview
-      * Reference documentation
-      * Setting up the UNIX evironment
-      * Running Cadence Virtuoso
-      * Quitting the session
-   * **[[analog_hierarchy|Design hierarchy]]**
-      * Introduction
-      * Libraries
-      * The ''cds.lib'' file
-      * Cells
-      * Cell views
-      * Using the Library Manager
-      * Creating a new library
-      * Creating a new cell
-      * Opening an existing cell
-      * Copying and deleting
-      * Managing libraries with the Library Path Editor
-   * **[[analog_cdsenv|Cadence setup files]]**
-      * Introduction
-      * Reference documentation
-      * ''.cadence'' directories
-      * ''cds.lib'' library definition file
-      * ''.cdsinit'' and ''.cdsenv'' initialization files
-      * ''.cdsinit_tech''
-      * ''libInit.il''
-      * ''.simrc''
-      * ''.plotinit''
-      * ''display.drf''
-      * [[analog_cdsenv#bindkeys|Bindkeys]]
-      * Customization examples
-   * **[[analog_schematic_tutorials|Basic analog design tutorials]]**
-      * Introduction
-      * Tutorial 1 - Basic NMOS characteristics
-      * Tutorial 2 - Common-source amplifier
-      * Tutorial 3 - The CMOS inverter
-      * Tutorial 4 - A two stage OPAMP with Miller compensation
-      * Tutorial 5 - ...
-      * Tutorial 6 - ...
-   * **[[analog_simref|Simulation references]]**
-      * [[vlsi:analog_simref#introduction|Introduction]]
-      * Analyses overview
-      * [[vlsi:analog_simref#power_consumption_evaluation|Power consumption evaluation]]
-      * [[vlsi:analog_simref#ADE_simulation_options|ADE simulation options]]
-      * ....
-   * **[[analog_techniques|Design techniques]]**
-      * Introduction
-      * MOS small signal model validity
-      * Analog design in very deep submicron technologies
-      * Rules of thumb for transistor sizing
-      * Some standard analog topologies
-   * **[[analog_bad|Bad analog design practices]]**
-      * Introduction
-      * ...
-   * **[[analog_advancedsim|Advanced analog design simulations]]**
-      * Introduction
-      * Getting started with ADE XL
-      * Reference documentation
-      * Corner analysis
-      * Monte Carlo simulations
-   * **[[analog_verilogA|Creating analog behavioral models with Verilog-A]]**
-      * Introduction
-   * **[[analog_ocean|Running simulations using OCEAN]]**
-      * Introduction
-   * **[[analog_layout_intro|Layout (an introduction)]]**
-      * Introduction
-      * Tools overview
-      * Reference documentation
-      * Environment setup
-      * Load standard bindkeys
-      * Starting Cadence Virtuoso Layout Editor L/XL
-      * Setting user preferences
-      * The Layer Palette
-   * **[[analog_layout_tutorials|Basic layout tutorials]]**
-      * Introduction
-      * Create a ruler
-      * Draw a simple metal layer
-      * Edit objects
-      * Merge layers
-      * View the layer stack
-      * Create a text label
-      * Create a pin
-   * **[[analog_layout_pcells|Working with parametrized cells]]**
-      * Introduction
-      * Substrate contacts
-      * NMOS layout
-      * PMOS layout
-   * **[[analog_layout_techniques|Layout techniques]]**
-      * Introduction
-      * Multi-finger transistors
-      * Common centroid layout
-      * Latch-up
-   * **[[analog_layout_examples|Standard layout examples]]**
-      * Inverter layout
-      * Common source amplifier
-      * NAND gate
-      * NOR gate
-      * Differential pair
-      * Ring oscillator
-   * **[[analog_layout_verification|Physical verification]]**
-      * Introduction
-      * Tools overview
-      * Design rules
-      * Design Rule Check (DRC)
-      * Electrical Rule Check (ERC)
-      * Layout-versus-Schematic (LVS)
-   * **[[analog_layout_assura|Assura tutorial]]**
-      * Introduction
-      * Documentation
-      * Environment setup
-      * Assura DRC
-      * Assura LVS
-      * Assura QRC
-   * **[[analog_layout_calibre|Calibre tutorial]]**
-      * Introduction
-      * Documentation
-      * Environment setup
-      * Calibre DRC
-      * Calibre LVS
-      * Calibre CRX
-   * **[[analog_layout_postsim|Post-Layout simulations]]**
-      * Introduction
-      * Parasitic extraction
-      * Simulation of the extracted netlist
-   * **[[ analog_howtos|HowTo's]]**
-   * **[[vlsi:analog_faqs|FAQs]]**
-**Keywords:**
-====== ======
-\\
-----
-\\
-Maintainers: [[lattuca@NOSPAMto.infn.it|Alessandra Lattuca]], [[pacher@NOSPAMto.infn.it|Luca Pacher]]\\
-Last update: [[pacher@NOSPAMto.infn.it|Luca Pacher]] - Arp 10, 2013