Power consumption evaluation in Cadence Virtuoso
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Contents
Keywords: power consumption
Introduction
example using a simple CMOS inverter testbench (P = 1/2CV^2 Vdd is a well known result)
Pavg = VDD x Iavg
VAR("Vdd")*average(IT("/Mx/D"))
Testbench schematic
create a CMOS inverter schematic as described in the CMOS inverter tutorial
Simulation setups
ADE L ⇒ Outputs ⇒ Save All..
Static power
Dynamic power
Average power
References
http://wiki.usgroup.eu/wiki/public/tutorials/powermeasure
http://wiki.usgroup.eu/wiki/_media/public/tutorials/powermeasure.pdf
http://www.egr.msu.edu/classes/ece410/mason/files/guide-power.pdf
http://www.ece.ncsu.edu/asic/ece733/hw/energy.pdf
http://www.seas.gwu.edu/~vlsi/ece218/SPRING/reference/lab6_power_dissipation.pdf