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http://webcast.berkeley.edu/playlist#c,d,Electrical_Engineering,ECD4C75518947B4347 (2011)

Course archive:

http://www-inst.eecs.berkeley.edu/~ee141/archives.html

Lecture notes:
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_s10/schedule.html

Lecture videos from YouTube:

• Lecture 1 - Course introduction, design methodologies, Moore's law, scaling | slides
• Lecture 2 - Design metrics (intro), CMOS processes, die cost, yield, VTC and noise margins | slides
• Lecture 3 - Design metrics (cont'd), delay, power dissipation, energy | slides
• Lecture 4 - Layout, design rules, MOS switches, CMOS inverter | slides
• Lecture 5
• Lecture 6
• Lecture 7
• Lecture 8
• Lecture 9
• Lecture 11

Lecture material and course home page:
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f10/
http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f10/schedule.html

Webcast home page:
http://webcast.berkeley.edu/playlist#c,d,Electrical_Engineering,EC4D6B92BD3AC8D9B4

Lecture videos from YouTube:

• Lecture 1 - Course introduction, history, Moore's law
• Lecture 2 - IC basics, manufacturing and cost
• Lecture 3 - CMOS inverter, design metrics (noise margins, delay, power and energy)
• Lecture 4 - Design metrics, static CMOS gates
• Lecture 5 - Layout, design rules, silicon memories, basic six-transistor SRAM cell
• Lecture 6 - SRAM design (intro), CMOS inverter delay optimization
• Lecture 7 - CMOS complex gates design, Elmore delay, logical effort
• Lecture 8 - Logical effort (contd.), decoder design, power
• Lecture 9 - MOS transistor modelling (basic square law, velocity saturation)
• Lecture 10 - Inverter VTC, inverter sizing, process variations and corners, MOS capacitances (bad video quality)
• Lecture 11 - MOS capacitances (contd.), delay calibration
• Lecture 12 - Delay calibration (contd.), slope analysis
• Lecture 13 - Power consumpion, leakage, sub-threshold conduction
• Lecture 14 - Sub-threshold conduction (contd.), threshold variations, introduction to STD cells design and layout
• Lecture 15 - Euler paths, basic layout techniques (multifingers), delay minimization, interconnections (delay, capacitance)
• Lecture 16 - Interconnections (contd.), wire resistance, RC delay model, SRAM circuit design
• Lecture 17 - SRAM design (contd.), power in basic CMOS gates (switching activity), clock, glitching, energy-performace space, sensitivity
• Lecture 18 - Sensitivity (contd.), CMOS transistor scaling, interconnect scaling, ratioed logic
• Lecture 19 - Ratioed logic (contd.), differential cascode voltage switch logic, pass-transistor logic, transmission gate
• Lecture 20 - Transmission gate (contd.), multiplexer, dynamic logic
• Lecture 21 - Full adder design techniques (static, dynamic)
• Lecture 22 - Full adder design (contd.), multipliers
• Lecture 23 - Domino logic
• Lecture 24 - Domino logic (contd.), introduction to sequential circuits, latches and FlipFlops, setup/hold time
• Lecture 25 - Layout parasitics, C2MOS latches and FlipFlops, three-state latches and FlipFlops, timing and clock modelling for synchronous design
• Lecture 26 - Timimg and clock modelling for synchronous design (contd.), clock distribution
• Lecture 27 - Clock distribution (contd.), chip packaging, ESD protection, I/O PADs, IR drops, electromigration, power distribution, ROM cells

Last update: Luca Pacher - Jul 28, 2014