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====== Part IV - Introduction to mixed-signal IC design ======

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== Contents ==



====== Introduction ======

Mixed-signal = design entry and circuit simulation with a mixture of schematic/SPICE description 
and HDL description 



[[http://en.wikipedia.org/wiki/Mixed-signal_integrated_circuit]]

[[http://www.cems.uvm.edu/~txia/cadence.htm]]

[[http://jcatsc.com/pages/courses/ee536a.php]]

[[http://www2.ece.ohio-state.edu/~bibyk/ece822/MSDK_July_2003.pdf‎]] \\
[[http://www2.ece.ohio-state.edu/~bibyk/ee720/ee720.htm]]           \\
[[http://www2.ece.ohio-state.edu/~bibyk/ece822/ece822.htm]]



Typical examples: Phase Locked Loop circuits (PLLs), A/D and D/A converters


EUROPRACTICE training references:

   * //[[http://www.europractice.stfc.ac.uk/training/|Introduction to Analogue and Mixed Signal IC Design]]//
   * //[[http://www.msc.stfc.ac.uk/msc/Training_Courses/|Mixed Signal IC Design and Implementation]]//





Design infrastructure: Verilog-A HDL, AMS simulator, config view, INCISIVE package


====== Creating analog behavioral models with Verilog-A ======




===== Reference documentation =====

===== Tutorials =====  

un tutorial [[ http://asic.co.in/Index_files/tutorials/verilog_a_tutorial_p1.htm | here ]]

un altro [[ http://www.ee.siue.edu/~jwade/tutorial/cadence_mixed-signal/ams_tutorial.html | here ]]




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