====== Digital synthesis with Cadence RTL Compiler (RC) ======

[ __[[vlsi:workbook:digital#contents|Back to index]]__ ]
[ __[[vlsi:workbook:digital:syn#contents|Contents]]__ ]
[ __[[vlsi:workbook:digital:syn:tmp|/tmp]]__ ]


== Contents ==

   * Introduction
   * Tools overview and documentation
   * ...
   * Tutorials



**Keywords:**


====== Introduction ======



A complete tutorial:

[[http://www.siue.edu/~gengel/ece484LabMaterial/RTLsynthesisTut.pdf]]

===== Getting started with Cadence RTL Compiler (RC) =====

**RTL Compiler** for //logic synthesis//

Documentazione:

''<sub>/usr/cadence/RC_9.10/doc</sub>''

Eseguibili in 

''/usr/cadence/RC_9.10/tools/bin''

type at the command line 

<code>
rc [-gui] 
</code>

<code>
rc -help
</code>

<code>
rc -help >> ./doc/rc.help
</code>

with no & !

the console this time is the initial window from which you
launched rc (that's why it had to be launched in the foreground).
Infatti poi il prompt della shell UNIX diventa

<code>
rc:/>
</code>


<code>
rc:/> help
</code>

<code>
rc:/> help <command>
</code>


Per uscire dalla GUI:

**RC GUI => File => Exit GUI**

per quittare RC:

<code>
rc:/> exit
</code>


**RC GUI => File => Source Script**

<code>
rc:/> source rtl.tcl
</code>



====== SDC clock definition ======

<code>
rc:/> dc::create_clock -help

Usage: create_clock [-add] [-name <string>] [-comment <string>] [-domain <string>] -period <float>
           [-waveform <float>+] [-apply_inverted <port|pin>+] [<port|pin>+]

    [-add]:
        should the sources add or overwrite 
    [-name <string>]:
        name of the clock 
    [-comment <string>]:
        comment to be tagged with this command 
    [-domain <string>]:
        name of the clock domain for the clock 
    -period <float>:
        clock period 
    [-waveform <float>+]:
        waveform string 
    [-apply_inverted <port|pin>+]:
        sources of the clock that are inverted 
    [<port|pin>+]:
        sources that are not inverted 
</code>


Fo deteiled information use

<code>
rc:/> man dc::create_clock 
</code>



<code>
-waveform <f><loat...>         Specifies the rise and fall edge times of
                               the clock waveform over one clock period. The
                               first value corresponds to the first rising
                               transition after time zero. The numbers should
                               represent one full clock period. If you omit this
                               option, a default waveform is assumed: the leading
                               edge occurs at 0 and the trailing edge occurs at
                               the midpoint of the period, such that a symmetric
                               clock is generated.
</code>

====== Post-synthesis simulation ======

Just simulate the synthesized Verilog netlist with the original testbench !

You must include detailed references to the Verilog description (source file/compiled Verilog) 
of STD cells for the technology you are working with

<code>
irun technology.v synthesized.v tb_design.v
</code>



Complete tutorial:

[[http://www.siue.edu/~gengel/ece484LabMaterial/RTLsynthesisTut.pdf]]

====== ======
\\
----

Last update: [[pacher@NOSPAMto.infn.it|Luca Pacher]] - Mar 25, 2013
~~NOTOC~~