====== Getting started ======

[ __[[vlsi:workbook:digital#contents|Back to index]]__ ]

== Contents ==

   * Introduction
   * ...
   * ...


**Keywords:**



===== Introduction =====



digital IC design flow, HDL code, poi **synthesis** e poi **place-and-route** di una
netlist sintetizzata



[[http://en.wikipedia.org/wiki/Functional_verification]]




===== Functional verification with Incisive =====

**functional verification** significa **Incisive**, quindi codice SystemC, VHDL and Verilog che viene compilato (check della
sintassi) e simulato

**ncsim** e' il nome dell'eseguibile (come quando lancio virtuoso!) 

[[ http://en.wikipedia.org/wiki/NCSim | NCSim ]] wikipedia

ncvhdl => eseguibile da lanciare per compilare solo VHDL

ncvlog => eseguibile per Verilog/System Verilog

ncsc => System C

**ncsim** => eseguibile che lancia la GUI, VHDL/Verilog/SystemC tutto unificato

oppure **nclaunch**

Release: INCISIV102

===== Logic syntesis with Cadence RTL Counter =====

Digital IC design significa usare **Encounter RTL** (il sintetizzatore) per fare la **syntesis**
cioe' dato il codice VHDL/etc. disegnare lo schematico!

Il gioco e' mangiare codice VHDL sintetizzabile e produrre lo schematico al gate-level, a cui
corrisponde una **synthesized netlist**

===== Backend design with SOC Encounter =====

con **SOC Encounter**  **System On Chip (SOC)** quindi **Place and Route** tool

Essenzialmente mangia la netlist sintetizzata da RTL Compiler e genera il circuito

import the **synthesized netlist** (the result of RTL synthesis with RTL Compiler)

Lo si lancia con (without &)

<code>
encounter 
</code>

===== Digital implementation with Encounter Digital Implementation (EDI) =====

tool completo pe rfar tutto

===== Documentation Incisive functional verification platform =====

Come spiegato in [[ cdsdoc | here ]] in the twiki dare un 

<code>
cd ~/cadence/doc
mkdir Incisive_10.20
cd Incisive_10.20
find /usr/cadence/Incisive_10.20/doc -name '*.pdf' -exec ln -s {} . \;
</code>


Esempio sono: 


''<sub>/usr/cadence/Incisive_10.20/doc/nclaunch/nclaunch.pdf</sub>''


''<sub>/usr/cadence/Incisive_10.20/doc/ncvhdl/ncvhdl.pdf</sub>''


''<sub>/usr/cadence/Incisive_10.20/doc/ncvlog/ncvlog.pdf</sub>''
 
^     **Tool**       ^      **File**         ^                 **Location**                             ^
| NC Launch          | nclaunch.pdf          |''<sub>/usr/cadence/Incisive_10.20/doc/nclaunch   </sub>''|
| NC VHDL            | ncvhdl.pdf            |''<sub>/usr/cadence/Incisive_10.20/doc/ncvhdl     </sub>''|
| NC Verilog         | ncvlog.pdf            |''<sub>/usr/cadence/Incisive_10.20/doc/ncvlog     </sub>''|



===== Documentation RTL Compiler (RC) platform =====


<code>
cd ~/cadence/doc
mkdir RC_9.10
cd RC_9.10
find /usr/cadence/RC_9.10/doc -name '*.pdf' -exec ln -s {} . \;
</code>

''<sub>/usr/cadence/RC_9.10/doc/rc_user/rc_user.pdf</sub>''

''<sub>/usr/cadence/RC_9.10/doc/rc_comref/rc_comref.pdf</sub>''

''<sub>/usr/cadence/RC_9.10/doc/rcgui/rcgui.pdf</sub>''

 
^     **Document**                ^      **File**         ^                 **Location**                        ^
| RC User Guide                   | rc_user.pdf           |''<sub>/usr/cadence/RC_9.10/doc/rc_user      </sub>''|
| RC Command Rerefence            | rc_comref.pdf         |''<sub>/usr/cadence/RC_9.10/doc/rc_comref    </sub>''|
| RC GUI                          | rcgui.pdf             |''<sub>/usr/cadence/RC_9.10/doc/rcgui        </sub>''|

===== Documentation SOC Encounter =====


<code>
cd ~/cadence/doc
mkdir SOC_8.10
cd SOC_8.10
find /usr/cadence/SOC_8.10/doc -name '*.pdf' -exec ln -s {} . \;
</code>

''<sub>/usr/cadence/SOC_8.10/doc/<tool></sub>''





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Last update: [[pacher@NOSPAMto.infn.it|Luca Pacher]] - Mar 25, 2013
~~NOTOC~~