====== Verilog simulation tutorials ======

== Contents ==

   * Getting started with Incisive tools
   * Running a Verilog 'Hello world!' 
   * [[vlsi:workbook:digital:hdlsim:tutorials:inverter|Simulate a simple inverter gate in Verilog]]
   * Simulate a synchronizer


===== Getting started with Cadence Incisive tools =====

suite utilizzata: Incisive release 10.2

Documentazione in 

''<sub>/usr/cadence/Incisive_10.20/doc</sub>''

Eseguibili in 

''<sub>/usr/cadence/Incisive_10.20/tools/bin</sub>''


Incisive tutorial [[ http://www.ece.virginia.edu/~mrs8n/cadence/Simulation_Tutorial/sim_tutorial.html | here ]]

Importante! Cadence stesso fornisce un tutorial!


''<sub>/usr/cadence/Incisive_10.20/doc/iustutorial</sub>''

<code>
cd ~/cadence/tutorial/incisive
cp -r /usr/cadence/Incisive_10.20/doc/iustutorial/examples/files ./src
</code>


Stating NCLaunch:



<code>
nclaunch [options] &
</code>

<code>
nclaunch -help
</code>

<code>
nclaunch -help >> ./doc/nclaunch.help
</code>


===== Running a Verilog 'Hello world!' =====


Un semplice **hello world** program da runnare alla command line:

<code verilog>
// hello.v Verilog hello world program

module hello;

   initial
      begin
         $display("Hello world! \n");
         $finish;
      end

endmodule
</code>


E lo posso compilare/runnare da command line ad esempio richiamando Verilog-XL:

<code>
verilog hello.v
</code>

Questo produce un output del tipo

<code>
Tool:   VERILOG-XL      08.20.001-d   Oct 22, 2012  00:31:41

Copyright (c) 1995-2004 Cadence Design Systems, Inc.  All Rights Reserved.
Unpublished -- rights reserved under the copyright laws of the United States.

Copyright (c) 1995-2004 UNIX Systems Laboratories, Inc.  Reproduced with Permission.

THIS SOFTWARE AND ON-LINE DOCUMENTATION CONTAIN CONFIDENTIAL INFORMATION
AND TRADE SECRETS OF CADENCE DESIGN SYSTEMS, INC.  USE, DISCLOSURE, OR
REPRODUCTION IS PROHIBITED WITHOUT THE PRIOR EXPRESS WRITTEN PERMISSION OF
CADENCE DESIGN SYSTEMS, INC.
RESTRICTED RIGHTS LEGEND

Use, duplication, or disclosure by the Government is subject to
restrictions as set forth in subparagraph (c)(1)(ii) of the Rights in
Technical Data and Computer Software clause at DFARS 252.227-7013 or
subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted
Rights at 48 CFR 52.227-19, as applicable.

                Cadence Design Systems, Inc.
                555 River Oaks Parkway
                San Jose, California  95134

For technical assistance please contact the Cadence Response Center at
1-877-CDS-4911 or send email to support@cadence.com

For more information on Cadence's Verilog-XL product line send email to
talkv@cadence.com

Compiling source file "hello.v"
Highest level modules:
hello

Hello world! 

L8 "hello.v": $finish at simulation time 0
0 simulation events (use +profile or +listcounts option to count)
CPU time: 0.0 secs to compile + 0.0 secs to link + 0.0 secs in simulation
End of Tool:    VERILOG-XL      08.20.001-d   Oct 22, 2012  00:31:41
</code>





====== A simple inverter Verilog tutorial ======


Bla bla bla click [[ incisive_tutorial_inverter | here ]]


====== Simulate a synchronizer ======


Bla bla bla click [[ incisive_tutorial_synchronizer | here ]]


====== A simple multiplexer ======


Bla bla bla click [[ incisive_tutorial_multiplexer | here ]]



====== Create a D Flip-Flop ======

Bla bla bla click [[ incisive_tutorial_dff | here ]]

====== RTL simulation using Verilog-XL compiler  ======

Anziche' usare nclaunch posso usare **Verilog-XL** e visualizzare le forme d'onda con **SimVision**

L'eseguibile e' sotto Incisive in


''<sub>$IUS_DIR/tools/bin/verilog</sub>''


<code>
verilog -help
</code>


Documentazione (Verilog-XL User Guide) sotto

''<sub>$IUS_DIR/doc/vloguser</sub>''

Posso fare tutto senza gui con

<code>
verilog main.v test_main.v
</code>

Attenzione all'ordine! che conta!

Pay attention when specifying the files names. The files have to be specified in a
particular order such that the lower-level modules are compiled before the higher-level modules.
The testbench would be the last item to be compiled.


Oppure da Cadence IC posso usare la Verilog Integration offerta da IC:

**CIW => Tools => NC-Verilog...**

or from **Schematic Editor L => Launch => Simulation => NC-Verilog**

{{:vlsi:virtuoso_ncverilog_integration.png}}


Documentazione in (ncveruser.pdf):

''<sub>/usr/cadence/IC_6.1.5/doc/ncveruser</sub>''



web tutorial [[ http://nanolab.ece.tufts.edu/docs/tutorial/verilog.html | here ]]



DFF example:

<code verilog>
// dff.v Verilog code

`timescale 1ns/100ps

module DFF(D, clk, Q);
   input D;
   input clk;
   output Q;

   reg Q;
   always @ (posedge clk)
      Q <= #2 D;

endmodule
</code>



MUX example:


Senza ritardi:

<code verilog>
module MUX2(input A, B, select, output W);
   assign W = (A & ~select) | (B & select);
endmodule
</code>


Con i ritardi, per vedere i **glitches**

<code verilog>

`timescale 1ns/100ps

module MUX2(input A, B, select, output W);
   
   assign #6 n = ~select;
   assign #3 m = A & select; 
   assign #3 p = B & n;
   assign #2 W = m | p;

endmodule
</code>


Sincronizzatore:

<code verilog>
// synch.v Verilog code

`timescale 1ns/100ps

module SYNCHRONIZER(input clk, adata, output reg synchdata);
   always @ (posedge clk)
      if ( adata == 0) synchdata <= 0;
      else synchdata <= 1;
endmodule
</code>