
<code>
cd ~/cadence/tutorials/incisive/
mkdir inverter
cd inverter
mkdir src
cd src
</code>


===== Preparing the Verilog source code =====

Quindi creare i files inverter.v e inverter_test.v:


<code verilog>
// inverter.v 
// Verilog code to describe a simple inverter
 
`timescale 1ns/100ps   // time unit and time precision

module INV2(in, out);  // module definition
   
   input in;   // port definitions
   output out;

   // primitive statement
   not (out, in);   
   
   //concurrent assignment
   //assign #2 out = ~in;  

endmodule
</code>

Poi il testbench

<code verilog>
// inverter_test.v
// testbench module for the inverter

`timescale 1ns/100ps   // time unit and time precision

module inv_test;   // module definition

   reg in;   // input and output 
   wire out;

   INV2 U1(in, out);   // inverter instantiation

   initial 
      begin
         in = 1'b0;      // input values
         #25 in = 1'b1;
         #75 in = 1'b0;
         #35 in = 1'b1;
         #100 $finish;   // end simulation
      end

endmodule
</code>

===== Start NCLaunch =====


<code>
nclaunch [-new] [-single] [-work]
</code>

Infine lanciare NCLaunch:

<code>
nclaunch -new &
</code>


{{:vlsi:nclaunch_new.png}}

Poi si apre NCLaunch con i files gia' caricati:

{{:vlsi:nclaunch_getting_started.png?780}}


Utilizzare **VIM** text editor!

Example:

inv.v e inv_test.v files can be found [[ | here ]] and [[ | here ]]


In single-step richiama irun

''<sub>/usr/cadence/Incisive_10.20/tools/bin/irun</sub>''


**NCLaunch => File => Switch to Single Step/Switch to Multiple Step**


Documentazione accessibile anche da

**NCLaunch => Help => NCLaunch User Guide**

e soprattutto i video-tutorials!

**NCLaunch => Help => Tutorials**


Uscire e chiudere:

**NCLaunch => File => Exit**

Design directory and work library:

**NCLaunch => File => Set Design Directory**

===== Compiling the source files =====

Compilazione:

**NCLaunch => Tools => VHDL Compiler/Verilog Compiler**

Notare che e' solo una via grafica per settare opzioni della riga di comando di ncvhdl:

<code>
ncvhdl [options] fileName.vhd (.vhdl)
</code>

<code>
ncvhdl -help > ~/cadence/doc/ncvhdl.help
</code>


Stessa pasta per ncvlog:

<code>
ncvlog [options] fileName.v
</code>

<code>
ncvlog -help > ~/cadence/doc/ncvlog.help
</code>


{{:vlsi:ncvlog_compiling_source_files.png?780}}

===== Elaboration =====

Selezionare **worklib => inv_test** e poi 
**NCLaunch => Tools => Elaborator**

Anche qui maschera cosa succede poi alla riga di comando:

<code>
ncelab [options] fileName
</code>


<code>
ncelab -help > ~/cadence/doc/ncelab.help
</code>


===== Simulate the design =====

**NCLaunch => Tools => Simulator**

che setta le opzioni di ncsim:

<code>
ncsim [options] fileName
</code>

<code>
ncsim -help > ~/cadence/doc/ncsim.help 
</code>


===== Plot waveform with SimVision =====

Design Browser di SimVision:

{{:vlsi:design_browser_1.png?750}}

SimVision console:


{{:vlsi:simvision_waveforms_no_delays.png?780}}


Posso modificare il codice e includere i delays:

<code>
   assign #2 out = ~in;
</code>

{{:vlsi:simvision_waveforms_with_delays.png?780}}