====== SystemVerilog references ====== [ __[[vlsi:home|Home]]__ ] [ __[[vlsi:workbook|Design WorkBook]]__ ] [ __[[vlsi:resources:books|Books]]__ ] //IEEE std 1800-2012// \\ [[http://www.eda.org/sv/SystemVerilog_3.1a.pdf|SystemVerilog 3.1a Language Reference Manual]] //OVM/UVM User's Guide// \\ ====== Syntax highlighting for the Gedit text editor ====== **1.** make a copy of the Verilog language style ''/usr/share/gtksourceview-2.0/language-specs/verilog.lang'' **2.** modify the language id as and **3.** change the default file extension *.sv **4.** add new SystemVerilog reserved words by following the XML syntax word